Growing adoption of Artificial Intelligence (AI) in almost every industrial sector has provided an impetus to innovations that can improve the performance of various systems that are commonly used for implementing the AI technology. A programmable chip and in-memory-computing processor architecture has been presented by researchers at Princeton University, which can be demonstrated in a 65nm CMOS technology.
The chip can be programmed by using any standard programming language and finds applications in most electronic products, such as watches and smartphones. Researchers have incorporated the in-memory computing technique to eliminate a technological and computational bottleneck in the chip and reduce the energy as well as time taken by the chip to transfer data from the chip memory.
The researchers have modified the basic properties of computation to build features of this chip, such as high-performance computing, faster speed, and improved energy efficiency. The researchers claim that this chip can perform remarkably better and a thousand times faster as compared to conventional computing chips.
Earlier, the researchers had collaborated with Analog Devices Inc., an American multinational semiconductor company that has an expertise in signal processing technology, to discover a way to fabricate circuitry for in-memory computing. However, due to the limited capacity of the chip, they failed to integrate all the components of the most recent model of the programmable chip.
The announcement of the new chip reports that charge-domain in-memory computing has been the focus for the researchers to successfully incorporate an in-memory-computing accelerator in the architecture of a programmable chip, where the architecture can be linked to the embedded CPU for the accelerator. This chip demonstrates maximum computational accuracy, which addresses the modern needs of computational operations that are performed in most modern applications.
“In the recent years, in-memory computing technology has been incorporated across a variety of industrial sectors due to its energy and speed benefits in computational applications,” said Naveen Verma, an associate professor of electrical engineering at Princeton University. “But in order to make it scalable and usable for system engineers towards computational AI applications, programmability becomes a necessity. In this chip, the central processor is separated from the computer architecture, which directly crunches data from the chip memory. This saves energy and improves its operational speed.”
The revolutionary research on the programmable chip suitable for AI applications was authored by Naveen Verma, Hongyang Jia, and Yinqi Tang, Jintao Zhang, and Hossein Valavi, who are graduate students in electrical engineering at Princeton University.